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features dual t1/e1 line interface optimized for mutiplexer applications low power consumption (typically 220mw per line interface) transmit driver performance monitors jitter attenuation in the transmit path matched impedance transmit drivers supports jtag boundary scan hardware mode derivative of the cs61584 general description the cs61582 is a dual line interface optimized for highly-integrated t1/e1 asynchronous or synchronous multiplexer applications such as sonet and sdh. each channel features individual control and status pins which eliminates the need for external microproc- essor support. the matched impedance drivers reduce power consumption and provide substantial return loss to insure superior t1/e1 pulse quality. the cs61582 provides two transmitter driver perform- ance monitor circuits and jtag boundary scan to enhance system testability and reliability. the cs61582 is a 5 volt device that is a hardware mode derivative of the cs61584. ordering information CS61582-IQ5, 64-pin tqfp, -40 to +85 c july 96 ds224pp1 1 crystal semiconductor corporation p. o. box 17847, austin, texas, 78760 (512) 445 7222 fax:(512) 445 7581 dual t1/e1 line interface cs61582 copyright ? crystal semiconductor corporation 1996 (all rights reserved) ttip1 tring1 rring1 rtip1 control tclk1 rclk1 jtag 4 refclk 1xclk t v + t g n d r v + r g n d d v + d g n d a v + a g n d bgref 2 2 2 2 3 2 clock generator tpos1 tneg1 rpos1 rneg1 los1 los2 pulse shaping circuitry clock & data recovery los detect jitter attenuator taos l o c a l l o o p b a c k 1 r e m o t e l o o p b a c k ttip2 tring2 rring2 rtip2 driver tclk2 rclk2 tpos2 tneg2 rpos2 rneg2 pulse shaping circuitry clock & data recovery taos l o c a l l o o p b a c k 1 r e m o t e l o o p b a c k jitter attenuator los detect driver performance monitor driver performance monitor mring1 mtip1 mring2 mtip2 dpm1 dpm2 reset clke taos1 lloop1 rloop1 con01 con11 con21 rloop2 lloop2 taos2 con02 con12 con22 receiver receiver driver
table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . 3 recommended operating conditions. . . . . . . . . . . . . . . . . . 3 digital characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 analog specifications receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 jitter attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 switching characteristics t1 clock/data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 e1 clock/data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 jtag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 general description overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 jitter attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 line control and monitoring . . . . . . . . . . . . . . . . . . . . . . . . 12 driver performance monitor . . . . . . . . . . . . . . . . . . 12 loss of signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 transmit all ones . . . . . . . . . . . . . . . . . . . . . . . . . . 12 local loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 remote loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 ds224pp1
absolute maximum ratings parameter symbol min max units dc supply (tv+1, tv+2, rv+1, rv+2, av+, dv+) (note 1) - 6.0 v input voltage (any pin) v in rgnd - 0.3 (rv+) + 0.3 v input current (any pin) (note 2) i in -10 10 ma ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c warning: operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. referenced to rgnd1, rgnd2, tgnd1, tgnd2, agnd, dgnd at 0v. 2. transient currents of up to 100 ma will not cause scr latch-up. recommended operating conditions parameter symbol min typ max units dc supply (tv+1, tv+2, rv+1, rv+2, av+, dv+) (note 3) 4.75 5.0 5.25 v ambient operating temperature t a -40 25 85 c power consumption t1 (notes 4 and 5) (each channel) t1 (notes 4 and 6) e1, 75 w (notes 4 and 5) e1, 120 w (notes 4 and 5) p c - - - - 310 220 275 275 - - - - mw mw mw mw refclk frequency t1 1xclk = 1 1.544 - 100 ppm 1.544 1.544 + 100 ppm mhz t1 1xclk = 0 12.352 - 100 ppm 12.352 12.352 + 100 ppm mhz e1 1xclk = 1 2.048 - 100 ppm 2.048 2.048 + 100 ppm mhz e1 1xclk = 0 16.384 - 100 ppm 16.384 16.384 + 100 ppm mhz notes: 3. tv+1, tv+2, av+, dv+, rv+1, rv+2 should be connected together. tgnd1, tgnd2, rgnd1, rgnd2, dgnd1, dgnd2, dgnd3 should be connected together. 4. power consumption while driving line load over operating temperature range. includes ic and load. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 5. assumes 100% ones density and maximum line length at 5.25v. 6. assumes 50% ones density and 300ft. line length at 5.0v. ds224pp1 3
digital characteristics (t a = -40 to 85 c; power supply pins within 5% of nominal) parameter symbol min typ max units high-level input voltage (note 7) v ih (dv+)-0.5 - - v low-level input voltage (note 7) v il --0.5v high-level output voltage (note 8) (digital pins) i out = -40 m a v oh (dv+)-0.3 - - v low-level output voltage (note 8) (digital pins) i out = 1.6 ma v ol --0.3v input leakage current (digital pins except j-tms, and j-tdi) -- 10 m a notes: 7. digital inputs are designed for cmos logic levels. 8. digital outputs are ttl compatible and drive cmos levels into a cmos load. analog specifications (t a = -40 to 85 c; power supply pins within 5% of nominal) parameter min typ max units receiver rtip/rring differential input impedance - 20k - w sensitivity below dsx-1 (0 db = 2.4 v) -13.6 - - db loss of signal threshold - 0.3 - v data decision threshold t1, dsx-1 (note 9) (note 10) e1 (note 11) (note 12) 60 55 45 40 65 - 50 - 70 75 55 60 % of peak allowable consecutive zeros before los 160 175 190 bits receiver input jitter 10 hz and below (note 13) tolerance (dsx-1, e1) 2 khz 10 khz - 100 khz 300 6.0 0.4 - - - - - - ui ui ui receiver return loss 51 khz - 102 khz (notes 14, 102 khz - 2.048 mhz 21, and 22) 2.048 mhz - 3.072 mhz 12 18 14 - - - - - - db db db jitter attenuator jitter attenuation curve t1 (notes 14 and 15) corner frequency e1 - - 4 5.5 - - hz hz attenuation at 10 khz jitter frequency (notes 14 and 15) - 60 - db attenuator input jitter tolerance (note 14) (before onset of fifo overflow or underflow protection) 28 43 - ui pk-pk notes: 9. for input amplitude of 1.2 v pk to 4.14 v pk 10. for input amplitude of 0.5 v pk to 1.2 v pk , and 4.14 v pk to 5.0 v pk 11. for input amplitude of 1.07 v pk to 4.14 v pk , 12. for input amplitude of 4.14 v pk to 5.0 v pk , 13. jitter tolerance increases at lower frequencies. refer to the receiver section. 14. not production tested. parameters guaranteed by design and characterization. 15. attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. circuit attenuates jitter at 20 db/decade above the corner frequency. output jitter can increase significantly when more than 28 ui?s are input to the attenuator. refer to the jitter attenuator section. 4 ds224pp1
analog specifications (t a = -40 to 85 c; power supply pins within 5% of nominal) parameter min typ max units transmitter ami output pulse amplitudes (note 16) e1, 75 w (note 17) e1, 120 w (note 18) t1, dsx-1 (note 19) 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 v v v recommended transmitter output load (note 16) t1 e1, 75 w e1, 120 w - - - 76.6 57.4 90.6 - - - w w w jitter added during 10 hz - 8 khz remote loopback 8 khz - 40 khz 10 hz - 40 khz broad band (note 20) - - - - 0.005 0.008 0.010 0.015 - - - - ui ui ui ui power in 2 khz band about 772 khz (notes 14 and 21) (dsx-1 only) 12.6 15 17.9 dbm power in 2 khz band about 1.544 mhz (notes 14 and 21)) (referenced to power in 2 khz band at 772 khz) (dsx-1 only) -29 -38 - db positive to negative pulse imbalance (notes 14 and 21) t1, dsx-1 e1, amplitude at center of pulse interval e1, width at 50% of nominal amplitude - -5 -5 0.2 - - 0.5 +5 +5 db % % transmitter return loss (notes 14, 21, and 22) 51 khz - 102 khz 102 khz - 2.048 mhz 2.048 mhz - 3.072 mhz 18 14 10 25 18 12 - - - db db db e1 short circuit current (note 23) - - 50 ma rms e1 and dsx-1 output pulse rise/fall times (note 24) - 25 - ns e1 pulse width (at 50% of peak amplitude) - 244 - ns e1 pulse amplitude e1, 75 w for a space e1, 120 w -0.237 -0.3 - - 0.237 0.3 v v notes: 16. using a transformer that meets the specifications in the applications section. 17. measured across 75 w at the output of the transmit transformer for con2/1/0 = 0/0/0. 18. measured across 120 w at the output of the transmit transformer for con2/1/0 = 0/0/1. 19. measured at the dsx-1 cross-connect for line length settings con2/1/0 = 0/1/0, 0/1/1, 1/0/0, 1/0/1, and 1/1/0 after the appropriate length of #22 abam cable specified in table 1. 20. input signal to rtip/rring is jitter free. values will reduce slightly if jitter free clock is input to tclk. 21. typical performance using the line interface circuitry recommended in the applications section. 22. return loss = 20 log 10 abs((z 1 +z 0 )/(z 1 -z 0 )) where z 1 =impedance of the transmitter or receiver, and z 0 =cable impedance. 23. transformer secondary shorted with 0.5 w resistor during the transmission of 100% ones. 24. at transformer secondary and measured from 10% to 90% of amplitude. ds224pp1 5
switching characteristics - t1 clock/data (t a = -40 to 85 c; power supply pins within 5% of nominal; inputs: logic 0 = 0v, logic 1 = dv+) (see figures 1, 2, and 3) parameter symbol min typ max units tclk frequency (note 25) f tclk - 1.544 - mhz tclk duty cycle t pwh2 /t pw2 30 50 70 % rclk duty cycle t pwh1 /t pw1 45 50 55 % rise time (all digital outputs) (note 26) t r - - 65 ns fall time (all digital outputs) (note 26) t f - - 65 ns rpos/rneg to rclk rising setup time t su1 - 274 - ns rclk rising to rpos/rneg hold time t h1 - 274 - ns tpos/tneg to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg hold time t h2 25 - - ns notes: 25. the maximum burst rate of a gapped tclk input clock is 8.192 mhz. the maximum gap size that can be tolerated on tclk is 28 uip-p. 26. at max load of 50 pf. switching characteristics - e1 clock/data (t a = -40 to 85 c; power supply pins within 5% of nominal; inputs: logic 0 = 0v, logic 1 = dv+) (see figures 1, 2, and 3) parameter symbol min typ max units tclk frequency (note 25) f tclk - 2.048 - mhz tclk duty cycle t pwh2 /t pw2 30 50 70 % rclk duty cycle t pwh1 /t pw1 45 50 55 % rise time (all digital outputs) (note 26) t r - - 65 ns fall time (all digital outputs) (note 26) t f - - 65 ns rpos/rneg to rclk rising setup time t su1 - 194 - ns rclk rising to rpos/rneg hold time t h1 - 194 - ns tpos/tneg to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg hold time t h2 25 - - ns 6 ds224pp1
any digital output t r t f 10% 10% 90% 90% figure 1. signal rise and fall characteristics rclk (clke = 1) t pwl1 t pwh1 rclk (clke =0) rpos rneg h1 t su1 t t pw1 figure 2. recovered clock and data switching characteristics tclk tpos tneg t su2 t h2 t pwh2 t pw2 figure 3. transmit clock and data switching characteristics ds224pp1 7
j-tck j-tms j-tdi j-tdo t cyc t dv t su t h figure 4. jag switching characteristics switching characteristics - jtag (t a = - 40 to 85 c; tv+, rv+ = nominal 0.3v; inputs: logic 0 = 0v, logic 1 = rv+) (see figure 4) parameter symbol min typ max units cycle time t cyc 200 - - ns j-tms/j-tdi to j-tck rising setup time t su 50 - - ns j-tck rising to j-tms/j-tdi hold time t h 50 - - ns j-tck falling to j-tdo valid t dv - - 50 ns 8 ds224pp1
overview the cs61582 is a dual line interface optimized for highly-integrated t1/e1 asynchronous or synchronous multiplexer applications such as sonet or sdh. one board design can support all t1/e1 short-haul modes by only changing component values in the receive and transmit paths (if refclk and tclk are externally tied together). all control of the device is achieved via external pins, eliminating the need for microprocessor support. the following pin control options are available on a per channel basis: line length se- lection, transmit all ones, local loopback, and remote loopback. the line driver generates waveforms compatible with e1 (ccitt g.703), t1 short haul (dsx-1) and t1 fcc part 68 option a (ds1). a single transformer turns ratio is used for all waveform types. the driver internally matches the imped- ance of the load, providing excellent return loss to insure superior t1/e1 pulse quality. an addi- tional benefit of the internal impedance matching is a 50 percent reduction in power consumption compared to implementing return loss using ex- ternal resistors that causes the transmitter to drive the equivalent of two line loads. the line receiver contains all the necessary clock and data recovery circuits. the jitter attenuator meets at&t 62411 require- ments when using a 1x or 8x reference clock supplied by either a crystal oscillator or external reference at the refclk input pin. transmitter the transmitter accepts data from a t1 or e1 system and outputs pulses of appropriate shape to the line. the transmit clock (tclk) and transmit data (tpos and tneg) are supplied synchronously. data is sampled on the falling edge of the tclk input. the configuration pins con[2:0] control trans- mitted pulse shapes, transmitter source impedance, and receiver slicing level as shown in table 1. typical output pulses are shown in figures 5 and 6. these pulse shapes are fully pre-defined by circuitry in the cs61582, and are fully compli- ant with appropriate standards when used with our application guidelines in standard installations. both channels must be operated at the same line rate (both t1 or both e1). note that the pulse width for part 68 option a (324 ns) is narrower than the optimal pulse width for dsx-1 (350 ns). the cs61582 auto- c o n 2 c o n 1 c o n 0 transmit pulse width at 50% amplitude transmit pulse shape receiver slicing level 0 0 0 0 0 1 244 ns (50%) 244 ns (50%) e1: square, 2.37 volts into 75 w e1: square, 3.00 volts into 120 w 50% 50% 0 1 0 324 ns (50%) ds1: fcc part 68 option a (0 db) 65% 0 1 1 350 ns (54%) dsx-1: 0-133 ft. / or ds1 fcc part 68 option a with undershoot 65% 1 0 0 350 ns (54%) dsx-1: 133-266 ft. 65% 1 0 1 350 ns (54%) dsx-1: 266-399 ft. 65% 1 1 0 350 ns (54%) dsx-1: 399-533 ft. 65% 1 1 1 350 ns (54%) dsx-1: 533-655 ft. 65% table 1. configuration selection ds224pp1 9
matically adjusts the pulse width based on the configuration selection. the transmitter impedance changes with the line length options in order to match the load imped- ance (75 w for e1 coax, 100 w for t1, 120 w for e1 shielded twisted pair), providing a minimum of 14 db return loss for t1 and e1 frequencies during the transmission of both marks and spaces. this improves signal quality by minimiz- ing reflections from the transmitter. impedance matching also reduces load power consumption by a factor of two when compared to the return loss achieved by using external resistors. the cs61582 driver will automatically detect an inactive tlck input (i.e., no valid data is being clocked to the driver). when this condition is de- tected, the driver is forced low (except during remote loopback) to output spaces and prevent ttip and tring from entering a constant trans- mit-mark state. when the transmit configuration established by con[2:0], taos, or lloop changes state, the transmitter stabilizes within 22 tclk bit peri- ods. the transmitter takes longer to stabilize when rloop1 or rloop2 is selected because the timing circuitry must adjust to the new fre- quency from rclk. when the transmitter transformer secondaries are shorted through a 0.5 ohm resistor, the transmit- ter will output a maximum of 50 ma-rms, as required by european specification bs6450. receiver the receiver extracts data and clock from the t1/e1 signal on the line interface and outputs clock and synchronized data to the system. the signal is detected differentially across the receive transformer and can be recovered over the entire range of short haul cable lengths. the transmit and receive transfomer specifications are identical and are presented in the applications section. as shown in table 1, the receiver slicing level is set at 65% for ds1/dsx-1 short-haul and at 50% for all other applications. 500 1.0 0.5 0 -0.5 0 250 750 1000 normalized amplitude cs61582 output pulse shape time (nanoseconds) ansi t1.102 specification figure 5. typical pulse shape at dsx-1 cross connect 269 ns 244 ns 194 ns 219 ns 488 ns nominal pulse 0 10 50 80 90 100 110 120 -10 -20 percent of nominal peak voltage g.703 specification figure 6. pulse mask at the 2048 kbps interface 10 ds224pp1
the clock recovery circuit is a second-order phase locked loop that can tolerate up to 0.4 ui of jitter from 10 khz to 100 khz without gener- ating errors (figure 7). the clock and data recovery circuit is tolerant of long strings of con- secutive zeros and will successfully recover a 1-in-175 jitter-free line input signal. recovered data at rpos and rneg is stable and may be sampled using the recovered clock rclk. the clke input determines the clock polarity where the output data is stable and valid as shown in table 2. when clke is low, rpos and rneg are valid on the rising edge of rclk. when clke is high, rpos and rneg are valid on the falling edge of rclk. clke data clock clock edge for valid data low rpos rneg rclk rclk rising rising high rpos rneg rclk rclk falling falling table 2. recovered data/clock options jitter attenuator the jitter attenuator is located in the transmit path of each channel to remove gapped clock jit- ter on tclk. figure 8 illustrates the typical jitter attenuation curve. the attenuator consists of a 64-bit fifo, a nar- row-band monolithic pll, and control logic. signal jitter is absorbed in the fifo which is de- signed to neither overflow nor underflow. if overflow or underflow is imminent, the jitter transfer function is altered to insure that no bit- errors occur. under this condition, jitter gain may occur and jitter should be attenuated exter- nally in a frame buffer. the jitter attenuator will typically tolerate 43 uis before the overflow/un- derflow mechanism occurs. if the jitter attenuator has not had time to "lock" to the aver- age incoming frequency (e.g., following a device reset) the attenuator will tolerate a minimum of 22 uis before the overflow/underflow mecha- nism occurs. the attenuator can accept a transmit clock with gaps 28 uis and a transmit clock burst rate of 8 mhz. when a loss of signal occurs, the last recovered frequency is not held and the output frequency be- comes the frequency of the reference clock. reference clock the cs61582 requires a reference clock with a minimum accuracy of 100 ppm for t1 and e1 applications. this clock can be either a 1x clock (i.e., 1.544 mhz or 2.048 mhz), or can be a 8x clock (i.e., 12.352 mhz or 16.384 mhz) as se- 10 1k 10k 1 100 100k 700 .1 1 10 100 .4 28 300 300 peak-to-peak jitter (unit intervals) jitter frequency (hz) cs61582 performance 138 at&t 62411 (1990 version) figure 7. minimum input jitter tolerance of receiver attenuation in db frequency in hz 0 10 20 30 40 50 60 1 10 100 1 k 10 k b) maximum attenuation lim it 62411 (1990 version) requirements a) minimum attenuation limit cs61582 performance figure 8. typical jitter transfer function ds224pp1 11
lected by the 1xclk pin. in systems with a jit- tered transmit clock, the reference clock should not be tied to the transmit clock and a separate external oscillator should drive the reference clock input. any jitter present on the reference clock will not be filtered by the jitter attenuator. power-up reset on power-up, the device is held in a static state until the power supply achieves approximately 60% of the power supply voltage. when this threshold is crossed, the device waits another 10 ms to allow the power supply to reach operating voltage and then calibrates the transmit and re- ceive circuitry. this initial calibration takes less than 20 ms but can occur only if refclk and tclk are present. the power-up reset performs the same functions as the reset pin. line control and monitoring line control and monitoring of the cs61582 is achieved using the control pins. the controls and indications available on the cs61582 are de- tailed below. device performance monitor to aid in the early detection and easy isolation of non-functioning links, the cs61582 is capable of monitoring the transmit driver performance and report when the driver is no longer opera- tional. the driver performance monitor consists of an activity detector that monitors the transmit- ted signal when mtip is connected to ttip and mring is connected to tring. the dpm out- put will go high when the differential inputs mtip and mring are inactive for 512 2 refclk periods. the dpm output returns low when the monitor senses a minimum 12.5% ones density signal over 175 75 bit periods with no more than 100 consecutive zeros. to increase the reliability of the performance monitor, it is sug- gested that the monitor inputs of one channel be connected the transmitter output pins of another channel or device. loss of signal the loss of signal (los) indication is detected by the receiver and reported by setting the los pin high. loss of signal is indicated when 175 15 consecutive zeros are received. the los condition is exited according to the ansi t1.231-1993 criteria that requires 12.5% ones density over 175 75 bit periods with no more than 100 consecutive zeros. note that bit errors may occur at rpos and rneg prior to the los indication if the analog input level falls below the receiver sensitivity. the los pin is set high when the device is reset or in power-up and returns low when data is re- covered by the receiver. transmit all ones transmit all ones is selected by setting the taos pin high. selecting taos causes continu- ous ones to be transmitted to the line interface on ttip and tring at the frequency of refclk. in this mode, the transmit data inputs tpos and tneg are ignored. a taos request overrides the data transmitted to the line inter- face during local and remote loopbacks. local loopback a local loopback is selected by setting the lloop pin high. selecting lloop causes the tclk, tpos, and tneg inputs to be looped back through the jitter attenuator to the rclk, rpos, and rneg outputs. data received at the line interface is ignored, but data at tpos and tneg continues to be transmitted to the line in- terface at ttip and tring. a taos request overrides the data transmitted to the line interface during local loopback. note that simultaneous selection of local and remote loopback modes is not valid. 12 ds224pp1
remote loopback a remote loopback is selected by setting the rloop pin high. selecting rloop causes the data received from the line interface at rtip and rring to be looped back through the jitter at- tenuator and retransmitted on ttip and tring. data transmitted at tpos and tneg is ignored, but data recovered from rtip and rring con- tinues to be transmitted on rpos and rneg. remote loopback is functional if tclk is ab- sent. a taos request overrides the data transmitted to the line interface during a remote loopback. note that simultaneous selection of lo- cal and remote loopback modes is not valid. reset pin the cs61582 is continuously calibrated during operation to insure the performance of the device over power supply and temperature. this con- tinuous calibration function eliminates the need to reset the line interface during operation. a device reset may be selected by setting the reset pin high for a minimum of 200 ns. the reset function initiates on the falling edge of re- set and requires less than 20 ms to complete. the control logic is initialized and the transmit and receive circuitry is calibrated if refclk and tclk are present. jtag boundary scan board testing is supported through jtag bound- ary scan. using boundary scan, the integrity of the digital paths between devices on a circuit board can be verified. this verification is sup- ported by the ability to externally set the signals on the digital output pins of the cs61582, and to externally read the signals present on the input pins of the cs61582. additionally, the manufac- turer id, part number and revision of the cs61582 can be read during board test using jtag boundary scan. as shown in figure 9, the jtag hardware con- sists of data and instruction registers plus a test access port (tap) controller. control of the tap is achieved through signals applied to the test mode select (j-tms) and test clock ( j-tck) input pins. data is shifted into the registers via the test data input (j-tdi) pin, and shifted out of the registers via the test data output (j-tdo) pin. both j-tdi and j-tdo are clocked at a rate determined by j-tck. the instruction register defines which data register is accessed in the mux j-tdi j-tck j-tms j-tdo jtag block boundary scan data register digital output pins digital input pins parallel latched output tap controller instruction (shift) register bypass data register device id data register parallel latched output figure 9. block diagram of jtag circuitry ds224pp1 13
shift operation. note that if j-tdi is floating, an internal pull-up resistor forces the pin high. jtag data registers (dr) the test data registers are the boundary-scan register (bsr), the device identification regis- ter (dir), and the bypass register (br). boundary scan register: the bsr is connected in parallel to all the digital i/o pins, and pro- vides the mechanism for applying/reading test patterns to/from the board traces. the bsr is 65 bits long and is initialized and read using the in- struction sample/preload. the bit ordering for the bsr is the same as the top-view package pin out, beginning with the los1 pin and mov- ing counter-clockwise to end with the rloop2 pin as shown in table 3. the input pins require one bit in the bsr and only one j-tck cycle is required to load test data for each input pin. the output pins have two bits in the bsr to de- fine output high, output low, or high impedance. the first bit (shifted in first) selects between an output-enabled state (bit set to 1) or high-imped- ance state (bit set to 0). the second bit shifted in contains the test data that may be output on the pin. therefore, two j-tck cycles are required to load test data for each output pin. the bi-directional pins have three bits in the bsr to define input, output high, output low, or high impedance. the first bit shifted into the bsr configures the output driver as high-imped- ance (bit set to 0) or active (bit set to 1). the second bit shifted into the bsr sets the output value when the first bit is 1. the third bit cap- tures the value of the pin. this pin may have its value set externally as an input (if the first bit is 0) or set internally as an output (if the first bit is 1). to configure a pad as an input, the j-tdi pattern is 0x0. to configure a pad as an output, the j-tdi pattern is 1x1. therefore, three j-tck cycles are required to load test data for each bi- directional pin. device identification register: the dir provides the manufacturer, part number, and version of the cs61582. this information can be used to verify that the proper version or revision number has been used in the system under test. the dir is 32 bits long and is partitioned as shown in figure 10. bsr bits pin name pad type 0-2 los1 bi-directional 2 3-5 tneg1 bi-directional 1 6 tpos1 input 7 tclk1 input 8-9 rneg1 output 10-11 rpos1 output 12-13 rclk1 output 14-16 dpm1 bi-directional 2 17-19 rloop1 bi-directional 1 20 lloop2 input 21-23 lloop1 bi-directional 1 24-26 taos1 bi-directional 1 27-29 taos2 bi-directional 1 30-32 con01 bi-directional 1 33-35 con02 bi-directional 1 36-38 con11 bi-directional 1 39-41 con12 bi-directional 1 42-44 con21 bi-directional 1 45 con22 input 46-48 dpm2 bi-directional 2 49-50 rclk2 output 51-52 rpos2 output 53-54 rneg2 output 55 tclk2 input 56 tpos2 input 57-59 tneg2 bi-directional 1 60-62 los2 bi-directional 2 63 clke input 64 rloop2 input 1. configure pad as an input. 2. configure pad as an output. table 3. boundary scan register 14 ds224pp1
data from the dir is shifted out to j-tdo lsb first. bypass register: the bypass register consists of a single bit, and provides a serial path between j-tdi and j-tdo, bypassing the bsr. this al- lows bypassing specific devices during certain board-level tests. this also reduces test access times by reducing the total number of shifts re- quired from j-tdi to j-tdo. jtag instructions and instruction register (ir) the instruction register (2 bits) allows the in- struction to be shifted into the jtag circuit. the instruction selects the test to be performed or the data register to be accessed or both. the valid instructions are shifted in lsb first and are listed below: ir code instruction 00 extest 01 sample/preload 10 idcode 11 bypass extest instruction: the extest instruction allows testing of off-chip circuitry and board- level interconnect. extest connects the bsr to the j-tdi and j-tdo pins. the normal path be- tween the cs61582 logic and i/o pins is broken. the signals on the output pins are loaded from the bsr and the signals on the input pins are loaded into the bsr. sample/preload instruction: the sam- ple/preload instructions allows scanning of the boundary-scan register without interfering with the operation of the cs61582. this instruc- tion connects the bsr to the j-tdi and j-tdo pins. the normal path between the cs61582 logic and its i/o pins is maintained. the signals on the i/o pins are loaded into the bsr. addi- tionally, this instruction can be used to latch values into the digital output pins. idcode instruction: the idcode instruction connects the device identification register to the j-tdo pin. the idcode instruction is forced into the instruction register during the test- logic-reset controller state.the default instruction is idcode after a device reset. bypass instruction: the bypass instruction connects the minimum length bypass register be- tween the j-tdi and j-tdo pins and allows data to be shifted in the shift-dr controller state. internal testing considerations note that the intest instruction is not sup- ported because of the difficulty in performing significant internal tests using jtag. the one test that could be easily performed us- ing an arbitrary clock rate on tclk and refclk is a local loopback with jitter attenu- ator disabled. however, this test provides limited fault coverage and is only useful in determining if the device had been catastrophically destroyed. alternatively, catastrophic destruction of the de- vice and/or surrounding board traces can be detected using extest. therefore, the intest instruction provides limited testing capability and was not included in the cs61582. jtag tap controller figure 11 shows the state diagram for the tap state machine. a description of each state fol- lows. note that the figure contains two main branches to access either the data or instruction bit #(s) function total bits 31-28 version number 4 27-12 part number 16 11-1 manufacturer number 11 0 constant logic 1 1 figure 10. device identification register msb lsb 31 28 27 12 11 1 0 00000000000000000011000011001001 (4 bits) (16 bits) (11 bits) ds224pp1 15
registers. the value shown next to each state transition in this figure is the value present at j-tms at each rising edge of j-tck. test-logic-reset state in this state, the test logic is disabled to continue normal operation of the device. during initiali- zation, the cs61582 initializes the instruction register with the idcode instruction. regardless of the original state of the controller, the controller enters the test-logic-reset state when the j-tms input is held high for at least five rising edges of j-tck. the controller re- mains in this state while j-tms is high. the cs61582 processor automatically enters this state at power-up. run-test/idle state this is a controller state between scan opera- tions. once in this state, the controller remains in the state as long as j-tms is held low. the instruction register and all test data registers re- tain their previous state. when j-tms is high and a rising edge is applied to j-tck, the con- troller moves to the select-dr state. select-dr-scan state this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if j-tms is held low and a rising edge is applied to j-tck when in this state, the controller moves into the capture- dr state and a scan sequence for the selected test data register is initiated. if j-tms is held high and a rising edge applied to j-tck, the controller moves to the select-ir-scan state. the instruction does not change in this state. capture-dr state in this state, the boundary scan register cap- tures input pin data if the current instruction is extest or sample/preload. the other test data registers, which do not have parallel in- put, are not changed. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-dr state if j-tms is high or the shift-dr state if j-tms is low. test-logic-reset run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 0 1 1 0 10 1 1 0 1 0 0 1 0 1 0 0 1 10 1 1 0 1 0 0 1 0 1 0 figure 11. tap controller state diagram 16 ds224pp1
shift-dr state in this controller state, the test data register con- nected between j-tdi and j-tdo as a result of the current instruction shifts data on stage to- ward its serial output on each rising edge of j-tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-dr state if j-tms is high or re- mains in the shift-dr state if j-tms is low. exit1-dr state this is a temporary state. while in this state, if j-tms is held high, a rising edge applied to j- tck causes the controller to enter the update-dr state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the pause-dr state. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. pause-dr state the pause state allows the test controller to tem- porarily halt the shifting of data through the test data register in the serial path between j-tdi and j-tdo. for example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. the controller remains in this state as long as j-tms is low. when j-tms goes high and a rising edge is applied to j-tck, the controller moves to the exit2-dr state. exit2-dr state this is a temporary state. while in this state, if j-tms is held high, a rising edge applied to j- tck causes the controller to enter the update-dr state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the shift-dr state. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. update-dr state the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in response to the extest and sample/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is latched into the parallel output of this register from the shift-reg- ister path on the falling edge of j-tck. the data held at the latched parallel output changes only in this state. all shift-register stages in the test data register selected by the current instruction retains their previous value during this state. the instructions does not change in this state. select-ir-scan state this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if j-tms is held low and a rising edge is applied to j-tck when in this state, the controller moves into the capture- ir state, and a scan sequence for the instruction register is initiated. if j-tms is held high and a rising edge is applied to j-tck, the controller moves to the test-logic-reset state. the in- struction does not change in this state. ds224pp1 17
capture-ir state in this controller state, the shift register con- tained in the instruction register loads a fixed value of "01" on the rising edge of j-tck. this supports fault-isolation of the board-level serial test data path. data registers selected by the current instruction retain their value during this state. the instruc- tions does not change in this state. when the controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-ir state if j-tms is held high, or the shift-ir state if j-tms is held low. shift-ir state in this state, the shift register contained in the instruction register is connected between j-tdi and j-tdo and shifts data one stage towards its serial output on each rising edge of j-tck. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. when the controller is in this state and a rising edge is applied to j-tck, the controller enters the exit1-ir state if j-tms is held high, or re- mains in the shift-ir state if j-tms is held low. exit1-ir state this is a temporary state. while in this state, if j-tms is held high, a rising edge applied to j- tck causes the controller to enter the update-ir state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the pause-ir state. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. pause-ir state the pause state allows the test controller to tem- porarily halt the shifting of data through the instruction register. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. the controller remains in this state as long as j-tms is low. when j-tms goes high and a rising edge is applied to j-tck, the controller moves to the exit2-ir state. exit2-ir state this is a temporary state. while in this state, if j-tms is held high, a rising edge applied to j- tck causes the controller to enter the update-ir state, which terminates the scanning process. if j-tms is held low and a rising edge is applied to j-tck, the controller enters the shift-ir state. the test data register selected by the current in- struction retains its previous value during this state. the instruction does not change in this state. update-ir state the instruction shifted into the instruction regis- ter is latched into the parallel output from the shift-register path on the falling edge of j-tck. when the new instruction has been latched, it becomes the current instruction. test data registers selected by the current in- struction retain their previous value. jtag application examples figures 12 and 13 illustrate examples of updat- ing the instruction and data registers during jtag operation. 18 ds224pp1
tck tms controller state tdi ir shift-register parallel output of ir parallel input to tdr tdr shift-register parallel output of tdr register selected tdo enable tdo act idcode new instruction old data instruction register inactive active inactive inactive = don't care or undefined parallel input to ir test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir pouse-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle exit1-ir shift-ir figure 12. jtag instruction register update ds224pp1 19
tck tms controller state tdi parallel input to ir ir shift-register parallel output of ir parallel input to tdr tdr shift-register register selected tdo enable tdo = don't care or undefined parallel output of tdr test-logic-reset run-test/idle select-dr-scan select-dr-scan capture-dr pouse-dr exit2-dr shift-dr update-dr run-test/idle exit1-dr shift-dr exit1-dr select-ir-scan idcode instruction old data test data register new data inactive active inactive inactive active figure 13. jtag data register update 20 ds224pp1
pin descriptions cs61582 64-pin tqfp top view 46 44 42 40 38 36 48 34 18 20 22 24 26 28 30 32 64 62 60 58 56 54 52 50 1 4 6 8 10 12 14 2 16 dv+ dgnd3 con02 con11 con12 con21 con22 dpm2 rclk2 rpos2 rneg2 tclk2 tpos2 tneg2 los2 clke j-tck j-tms ttip2 tv+2 tgnd2 tring2 mring2 mtip2 rtip2 rring2 rv+2 rgnd2 1xclk rloop2 refclk reset dgnd1 con01 taos2 taos1 lloop2 lloop1 rloop1 dpm1 rclk1 rpos1 rneg1 tclk1 tpos1 tneg1 los1 j-tdo dgnd2 j-tdi ttip1 tv+1 tgnd1 tring1 mring1 mtip1 rtip1 rring1 rv+1 rgnd1 agnd1 bgref agnd2 av+ ds224pp1 21
power supplies agnd1, agnd2 : analog ground (pins 21, 23) analog supply ground pins. av+ : analog power supply (pin 24) analog supply pin for the internal bandgap reference and timing generation circuits. bgref : bandgap reference (pin 22) this pin is used by the internal bandgap reference and must be connected to ground by a 4.99k w 1% resistor to provide an internal current reference. dgnd1, dgnd2, dgnd3 : digital ground (pins 57, 9, 55) power supply ground pins for the digital circuitry of both channels. dv+ : power supply (pin 56) power supply pin for the digital circuitry of both channels. rgnd1, rgnd2 : receiver ground (pins 20, 29) power supply ground pins for the receiver circuitry. rv+1, rv+2 : receiver power supply (pins 19, 30) power supply pins for the analog receiver circuitry. tgnd1, tgnd2 : transmit ground (pins 13, 36) power supply ground pins for the transmitter circuitry. tv+1, tv+2 : transmit power supply (pins 12, 37) power supply pins for the analog transmitter circuitry. t1/e1 data rclk1, rclk2 : receive clock (pins 1, 48) rpos1, rpos2 : receive positive data (pins 2, 47) rneg1, rneg2 : receive negative data (pins 3, 46) the receiver recovered clock and nrz digital data from rtip and rring is output on these pins. the clke pin determines the clock edge on which rpos and rneg are stable and valid as shown in table 2. a positive pulse (with respect to ground) received on rtip generates a logic 1 on rpos, and a positive pulse received on rring generates a logic 1 on rneg. rtip1, rtip2 : receive tip (pins 17, 32) rring1, rring2 : receive ring (pins 18, 31) the receive ami signal from the line interface is input on these pins. the recovered clock and data are output on rclk, rpos, and rneg. ttip1, ttip2 : transmit tip (pins 11, 38) tring1, tring2 : transmit ring (pins 14, 35) the transmit ami signal to the line interface is output on these pins. the transmit clock and data are input from tclk, tpos, and tneg. 22 ds224pp1
tclk1, tclk2 : transmit clock (pins 4, 45) tpos1, tpos2 : transmit positive data (pins 5, 44) tneg1, tneg2 : transmit negative data (pins 6, 43) the transmit clock and data are input on these pins. the signal is driven to the line at ttip and tring. data on tpos and tneg are sampled on the falling edge of tclk. an input on tpos causes a positive pulse to be transmitted at ttip and tring, while an input on tneg input causes a negative pulse to be transmitted at ttip and tring. oscillator 1xclk : one-times clock frequency select (pin 28) when 1xclk is set high, refclk must be a 1x clock (i.e., 1.544 mhz for t1 applications or 2.048 mhz for e1 applications). when 1xclk is set low, refclk must be an 8x clock (i.e., 12.352 mhz for t1 applications or 16.384 mhz for e1 applications). refclk : external reference clock input (pin 26) input reference clock for the receive and jitter attenuator circuits. when 1xclk is set high, refclk must be a 1x clock (i.e., 1.544 mhz 100 ppm for t1 applications or 2.048 mhz 100 ppm for e1 applications). when 1xclk is set low, refclk must be an 8x clock (i.e., 12.352 mhz 100 ppm for t1 applications or 16.384 mhz 100 ppm for e1 applications). the refclk input also determines the transmission rate when taos is asserted. control clke : clock edge (pin 41) controls the polarity of the recovered clock rclk. when clke is high, rpos and rneg are valid on the falling edge of rclk. when clke is low, rpos and rneg are valid on the rising edge of rclk. con01, con11, con21 : configuration for channel 1 (pins 58, 53, 51) con02, con12, con22 : configuration for channel 2 (pins 54, 52, 50) these pins configure the transmitter (pulse shape, pulse width, pulse amplitude, and driver impedance) and receiver (slicing level). the conx1 pins control channel 1 and the conx2 pins control channel 2. both channels must be configured to operate at the same data rate on the line interface (both t1 or both e1). lloop1, lloop2 : local loopback (pins 62, 61) a local loopback is enabled when lloop is high. during local loopback, the tclk, tpos, and tneg inputs are looped back through the jitter attenuator to the rclk, rpos, and rneg outputs. the data at tpos and tneg continues to be transmitted to the line interface unless overridden by a taos request. the inputs at rtip and rring are ignored. reset : reset (pin 25) a device reset is selected by setting the reset pin high for a minimum of 200 ns. the reset function initiates on the falling edge of reset and requires less than 20 ms to complete. the control logic is initialized and los is set high. ds224pp1 23
rloop1, rloop2 : remote loopback (pins 63, 27) a remote loopback is selected when rloop is high. the data received from the line interface at rtip and rring is looped back through the jitter attenuator and retransmitted on ttip and tring. data recovered from rtip and rring continues to be transmitted on rpos and rneg. data input on tpos and tneg is ignored. a taos request overrides the data transmitted at ttip and tring. taos1, taos2 : transmit all ones select (pins 60, 59) setting taos high causes continuous ones to be transmitted at the line interface on ttip and tring at the frequency determined by refclk. status dpm1, dpm2 : driver performance monitor alarm (pins 64, 49) the dpm alarm indication goes high when differential inputs mtip and mring are inactive for 512 2 refclk periods. the dpm alarm indication returns low when mtip and mring detect a minimum 12.5% ones density signal over 175 75 bit periods with no more than 100 consecutive zeros. mtip1, mtip2 : monitor tip (pins 16, 33) mring1, mring2 : monitor ring (pins 15, 34) the mtip and mring inputs may be connected to ttip and tring, to detect an inactive transmit driver. the mtip and mring inputs are differential and may be connected to either transmitter output. to increase the reliability of the performance monitor, it is suggested that the monitor inputs of one channel be connected the transmitter output pins of another channel or device. los1, los2 : loss of signal (pins 7, 42) the los indication goes high when 175 15 consecutive zeros are received on the line interface. the los indication returns low when a minimum 12.5% ones density signal over 175 75 bit periods with no more than 100 consecutive zeros is received. tes t j-tck : jtag test clock (pin 40) data on pins j-tdi and j-tdo is valid on the rising edge of j-tck. when j-tck is stopped low, all jtag registers remain unchanged. j-tms : jtag test mode select (pin 39) an active high signal on j-tms enables the jtag serial port. this pin has an internal pull-up resistor. j-tdi : jtag test data in (pin 10) jtag data is shifted into the device on this pin. this pin has an internal pull-up resistor. data must be stable on the rising edge of j-tck. j-tdo : jtag test data out (pin 8) jtag data is shifted out of the device on this pin. this pin is active only when jtag testing is in progress. j-tdo will be updated on the falling edge of j-tck. 24 ds224pp1
physical dimensions millimeters inches 64 1 dim d d e b a a l c 0.461 0.394 0.40 0.016 10.00 11.70 0.14 - 0.00 min 0.35 0.077 1.66 - max 0.26 0.70 0.177 0.006 - 0.00 min 0.014 0.003 0.068 - max 0.010 0.028 0.007 0.60 10.00 12.30 0.024 0.394 0.484 1 d d 1 e e 1 e e 0.461 0.394 10.00 11.70 10.00 12.30 0.394 0.484 1 a 1 a e b l terminal detail 1 c 1 0 12 0 12 64-pin tqfp ds224pp1 25
applications line interface figure a1 illustrates a typical connection diagram and table a1 lists the external components that are required in t1 and e1 applications. in the transmit line interface circuitry, capacitors c1 and c2 provide transmitter return loss. the 0.47 m f capacitor in series with the transformer primary prevents output stage imbalances from producing a dc current through the transformer that might saturate the transformer and result in an output level offset. in the receive line interface circuitry, resistors r1- r4 provide receive impedance matching and receiver return loss. the 0.47 m f capacitor to ground provides the necessary differential input voltage reference for the receiver. power supply as shown in figure a1, the cs61582 operates from a 5.0 volt supply. separate analog and digi- tal power supply and ground pins provide internal isolation. the tgnd, rgnd, and dgnd ground pins must not be more negative than agnd. it is recommended that all of the supply pins be con- av+ agnd1:2 bgref tv+1 tgnd1 rv+1 rgnd1 dv+ dgnd1:3 0.01 m f tclk1 tpos1 tneg1 rclk1 rpos1 rneg1 tclk2 tpos2 tneg2 rclk2 rpos2 rneg2 framer framer ttip1 tring1 1:1.15 rtip1 rring1 ttip2 tring2 rtip2 rring2 1:1.15 hardware control power supply clock generator channel 2 channel 1 transmit transmit 3 0.1 m f 1 m f + 0.1 m f tv+2 tgnd2 rv+2 rgnd2 22 m f + 0.1 m f 0.1 m f 0.1 m f 1:1.15 receive r3 r4 1:1.15 receive r1 r2 t1 t2 t3 t4 r3 5k w v cc 0.47 m f 0.47 m f refclk 1xclk reset clke rloop[1:2] taos[1:2] lloop[1:2] dpm[1:2] mtip[1:2] mring[1:2] los[1:2] con[0:2]2 con[0:2]1 c1 c2 0.47 m f 0.47 m f 2 3 3 2 2 2 22 2 2 figure a1. typical connection diagram data rate (mhz) refclk frequency (mhz) cable ( w )r1-r4 ( w ) c1-c2 (pf) 1xclk = 1 1xclk = 0 1.544 1.544 12.352 100 38.3 220 2.048 2.048 16.384 75 28.7 470 120 45.3 220 table a1. cs61582 external components 26 ds224pp1
nected together at the device. a 4.99k w 1% re- sistor must be connected from bgref to ground to provide an internal current reference. de-coupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits. a capacitor should be connected between each supply and its respective ground. for capaci- tors smaller than 1 m f, use mylar or ceramic capacitors and place them as close as possible to their respective power supply pins. wire-wrap bread boarding of the line interface is not recom- mended because lead resistance and inductance defeat the function of the de-coupling capacitors. crystal oscillator when a reference clock signal is not available, a cmos crystal oscillator operating at either the 1x or 8x rate can be connected at the refclk pin. the oscillator must have a minimum symme- try of 40-60% and minimum stability of 100 ppm for t1 and e1 applications. based on these specifications, some suggested crystal oscillators for use with the cs61582 are shown in table a2. transformers recommended transformer specifications are shown in table a3. based on these specifications, the transformers recommended for use with the cs61582 are listed in table a4. line protection secondary protection components can be added to the line interface circuitry to provide lightning surge and ac power-cross immunity. for addi- tional information on the different electrical safety standards and specific application circuit recommendations, refer to the crystal semicon- ductor application note "secondary line protection for t1 and e1 line cards." manufacturer part number contact number comclok ct31ch (800) 333-9825 cts cxo-65hg-5-i (815) 786-8411 m-tron mh26tad (800) 762-8800 saronix nth250a (800) 227-8974 notes: frequency tolerances are 32 ppm with a -40 to +85 c operating temperature range. all are 8-pin dip packages and can be tristated. table a2. suggested crystal oscillators turns ratio 1:1.15 step-up transmit 1:1.15 step-down receive primary inductance 1.5 mh min at 772 khz primary leakage inductance 0.3 m h max at 772 khz with secondary shorted secondary leakage inductance 0.4 m h max at 772 khz interwinding capacitance 18 pf max, primary to secondary et-constant 16 v- m s min table a3. transformer specifications ds224pp1 27
turns ratio manufacturer part number package type 1:1.15 pulse engineering pe-65388 1.5 kv through-hole, single pe-65770 1.5 kv through-hole, single extended temperature pe-65838 3.0 kv through-hole, single extended temperature pe-68674 1.5 kv surface-mount, dual extended temperature pe-65870 1.5 kv surface-mount, dual schott 67124840 1.5 kv through-hole, single extended temperature valor st5112 2.0 kv surface mount, dual table a4. recommended transformers schematic & layout review service confirm optimum schematic & layout before building your board. for our free review service call applications engineering. call: (512) 445-7222 28 ds224pp1
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